A digital signal computer, or digital signal processor (DSP), is a special purpose computer that is designed to optimize performance for digital signal processing applications, such as, for example, fast Fourier transforms, digital filters, image processing, signal processing in wireless systems, and speech recognition. Digital signal processors are typically characterized by real-time operation, high interrupt rates and intensive numeric computations. In addition, digital signal processor applications tend to be intensive in memory access operations and to require the input and output of large quantities of data. Digital signal processor architectures are typically optimized for performing such computations efficiently.
Digital signal processors may include components such as a core processor, a memory, a DMA controller, an external bus interface and one or more peripheral interfaces on a single chip or substrate. The components of the digital signal processor are interconnected by a bus architecture which produces high performance under desired operating conditions. The bus architecture may be configured to provide data to the core processor at a rate sufficient to minimize core processor stalling.
The instruction set of a digital signal processor typically includes both microcontroller instructions and DSP instructions. DSP instructions may involve complex computations and may need to run in real time to process received samples. Microcontroller instructions typically access relatively slow regions of memory, such as off-chip memory, wherein a fetch may require hundreds of core cycles. If the processor switches from execution of microcontroller instructions to a high priority task, such as DSP computations, the pipeline is flushed and the slow process values are stored. Any data that is committed but not yet written to the slow memory may utilize a store buffer. If the store buffer is filled with slow traffic to external memory, the high priority task is not able to do any store operations. However, the first thing an interrupt handler typically does is store values to memory. It is desirable to minimize latency in servicing the high priority task.
Another source of latency in servicing high priority tasks is a cache line fill operation. In the event of a cache miss, a cache line fill operation is initiated. Information missing from the cache is read from slower memory to a line fill buffer and then is transferred into the cache. If the cache line fill operation is in process at the time of an interrupt, servicing of the interrupt may be delayed because the line fill buffer is needed to load an interrupt handler. The cache line fill operation could be aborted, but this would reduce the performance of other applications.
Accordingly, there is a need for methods and apparatus for achieving low latency in servicing high priority tasks in a digital signal processor.